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[Other resource] micro uart

Description: 硬件uart源程序verilog HDL，即相关文档-hardware UART Verilog HDL source, that the relevant documents
Platform: | Size: 342886 | Author: 陈正一 | Hits:

[Other resource] uart-verilog-vhdl

Description: 拿verilog和vhdl编写的串口通信代码(可综合)-with vhdl and verilog prepared by the serial communication code (synthesis)
Platform: | Size: 295414 | Author: 刘索山 | Hits:

[Com Port] uart(Verilog)

Description: RS232的verilog源代码,如果需要的可以
Platform: | Size: 10421 | Author: 陈强 | Hits:

[Other resource] uart(Verilog)

Description: uart异步串口通信协议的源代码，用vhdl语言编写，并且有完整得测试文件
Platform: | Size: 11000 | Author: 阿军 | Hits:

[Other] u-uart

Description: UART verilog TX/RX OpenCores share
Platform: | Size: 5599 | Author: richman | Hits:

[VHDL-FPGA-Verilog] uart的verilog源代码

Description:

简化的uart设计：uart是一种广泛使用的串型数据传输协议，允许在串行链路上进行全双工通信。

Platform: | Size: 41472 | Author: yingkeli | Hits:

[Com Port] uart

Description: 串口通信的接收和发送数据的verilog编程，对每条语句有详细说明其实现的功能。
Platform: | Size: 484481 | Author: yiyi1223 | Hits:

[WinSock-NDIS] uart verilog

Description: 串口verilog UART,源码；串口verilog UART,源码
Platform: | Size: 6041 | Author: malesky@163.com | Hits:

[VHDL-FPGA-Verilog] cuart

Description: verilog编写的全功能串口-verilog programme of serial port
Platform: | Size: 5120 | Author: 刘陆陆 | Hits:

[VHDL-FPGA-Verilog] uart_verilog

Description: 包含UART口的VERILOG源程序，该程序在FPGA上验证通过，可作为芯片设计，或FPGA设计的一个完整IP核，硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.
Platform: | Size: 9216 | Author: 施向东 | Hits:

[VHDL-FPGA-Verilog] Uart

Description: fpga verilog语言，写的串口通讯，经测试完全没有问题-fpga verilog uart communication
Platform: | Size: 1988608 | Author: 孙祥龙 | Hits:

[VHDL-FPGA-Verilog] UART

Description: verilog写的串口程序，其功能完全最正确，带工程文件-verilog to write the serial program, its function is completely the right, with the project file
Platform: | Size: 433152 | Author: 潘政 | Hits:

[Windows Develop] UART

Description: UART loopback测试实例，接收PC端发送的UART数据，原数据返回给PC端，即loopback功能(The UART loopback test instance receives the number of UART sent by the PC side According to the original data returned to the PC side, that is, the loopback function)
Platform: | Size: 6258688 | Author: 航天梦 | Hits:

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[Other resource] micro uart

[Other resource] uart-verilog-vhdl

[Com Port] uart(Verilog)

[Other resource] uart(Verilog)

[Other] u-uart

[VHDL-FPGA-Verilog] uart的verilog源代码

[Com Port] uart

[WinSock-NDIS] uart verilog

[VHDL-FPGA-Verilog] cuart

[VHDL-FPGA-Verilog] uart_verilog

[VHDL-FPGA-Verilog] Uart

[VHDL-FPGA-Verilog] UART

[Windows Develop] UART

[VHDL-FPGA-Verilog] UART-master

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] uart

[Com Port] UART发送接收奇偶校验

[Other] FPAG UART Verilog

[VHDL-FPGA-Verilog] uart

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